
binary-tree:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400568 <_init>:
  400568:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40056c:	910003fd 	mov	x29, sp
  400570:	9400003a 	bl	400658 <call_weak_fn>
  400574:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400578:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400580 <.plt>:
  400580:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400584:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10040>
  400588:	f947fe11 	ldr	x17, [x16, #4088]
  40058c:	913fe210 	add	x16, x16, #0xff8
  400590:	d61f0220 	br	x17
  400594:	d503201f 	nop
  400598:	d503201f 	nop
  40059c:	d503201f 	nop

00000000004005a0 <malloc@plt>:
  4005a0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005a4:	f9400211 	ldr	x17, [x16]
  4005a8:	91000210 	add	x16, x16, #0x0
  4005ac:	d61f0220 	br	x17

00000000004005b0 <__libc_start_main@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005b4:	f9400611 	ldr	x17, [x16, #8]
  4005b8:	91002210 	add	x16, x16, #0x8
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__gmon_start__@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005c4:	f9400a11 	ldr	x17, [x16, #16]
  4005c8:	91004210 	add	x16, x16, #0x10
  4005cc:	d61f0220 	br	x17

00000000004005d0 <abort@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005d4:	f9400e11 	ldr	x17, [x16, #24]
  4005d8:	91006210 	add	x16, x16, #0x18
  4005dc:	d61f0220 	br	x17

00000000004005e0 <__isoc99_scanf@plt>:
  4005e0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005e4:	f9401211 	ldr	x17, [x16, #32]
  4005e8:	91008210 	add	x16, x16, #0x20
  4005ec:	d61f0220 	br	x17

00000000004005f0 <printf@plt>:
  4005f0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005f4:	f9401611 	ldr	x17, [x16, #40]
  4005f8:	9100a210 	add	x16, x16, #0x28
  4005fc:	d61f0220 	br	x17

0000000000400600 <putchar@plt>:
  400600:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400604:	f9401a11 	ldr	x17, [x16, #48]
  400608:	9100c210 	add	x16, x16, #0x30
  40060c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400610 <_start>:
  400610:	d280001d 	mov	x29, #0x0                   	// #0
  400614:	d280001e 	mov	x30, #0x0                   	// #0
  400618:	aa0003e5 	mov	x5, x0
  40061c:	f94003e1 	ldr	x1, [sp]
  400620:	910023e2 	add	x2, sp, #0x8
  400624:	910003e6 	mov	x6, sp
  400628:	580000c0 	ldr	x0, 400640 <_start+0x30>
  40062c:	580000e3 	ldr	x3, 400648 <_start+0x38>
  400630:	58000104 	ldr	x4, 400650 <_start+0x40>
  400634:	97ffffdf 	bl	4005b0 <__libc_start_main@plt>
  400638:	97ffffe6 	bl	4005d0 <abort@plt>
  40063c:	00000000 	.inst	0x00000000 ; undefined
  400640:	00400ea8 	.word	0x00400ea8
  400644:	00000000 	.word	0x00000000
  400648:	00400ef8 	.word	0x00400ef8
  40064c:	00000000 	.word	0x00000000
  400650:	00400f78 	.word	0x00400f78
  400654:	00000000 	.word	0x00000000

0000000000400658 <call_weak_fn>:
  400658:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10040>
  40065c:	f947f000 	ldr	x0, [x0, #4064]
  400660:	b4000040 	cbz	x0, 400668 <call_weak_fn+0x10>
  400664:	17ffffd7 	b	4005c0 <__gmon_start__@plt>
  400668:	d65f03c0 	ret
  40066c:	00000000 	.inst	0x00000000 ; undefined

0000000000400670 <deregister_tm_clones>:
  400670:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  400674:	91012000 	add	x0, x0, #0x48
  400678:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  40067c:	91012021 	add	x1, x1, #0x48
  400680:	eb00003f 	cmp	x1, x0
  400684:	540000a0 	b.eq	400698 <deregister_tm_clones+0x28>  // b.none
  400688:	90000001 	adrp	x1, 400000 <_init-0x568>
  40068c:	f947cc21 	ldr	x1, [x1, #3992]
  400690:	b4000041 	cbz	x1, 400698 <deregister_tm_clones+0x28>
  400694:	d61f0020 	br	x1
  400698:	d65f03c0 	ret
  40069c:	d503201f 	nop

00000000004006a0 <register_tm_clones>:
  4006a0:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  4006a4:	91012000 	add	x0, x0, #0x48
  4006a8:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  4006ac:	91012021 	add	x1, x1, #0x48
  4006b0:	cb000021 	sub	x1, x1, x0
  4006b4:	9343fc21 	asr	x1, x1, #3
  4006b8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4006bc:	9341fc21 	asr	x1, x1, #1
  4006c0:	b40000a1 	cbz	x1, 4006d4 <register_tm_clones+0x34>
  4006c4:	90000002 	adrp	x2, 400000 <_init-0x568>
  4006c8:	f947d042 	ldr	x2, [x2, #4000]
  4006cc:	b4000042 	cbz	x2, 4006d4 <register_tm_clones+0x34>
  4006d0:	d61f0040 	br	x2
  4006d4:	d65f03c0 	ret

00000000004006d8 <__do_global_dtors_aux>:
  4006d8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006dc:	910003fd 	mov	x29, sp
  4006e0:	f9000bf3 	str	x19, [sp, #16]
  4006e4:	d0000093 	adrp	x19, 412000 <malloc@GLIBC_2.17>
  4006e8:	39412260 	ldrb	w0, [x19, #72]
  4006ec:	35000080 	cbnz	w0, 4006fc <__do_global_dtors_aux+0x24>
  4006f0:	97ffffe0 	bl	400670 <deregister_tm_clones>
  4006f4:	52800020 	mov	w0, #0x1                   	// #1
  4006f8:	39012260 	strb	w0, [x19, #72]
  4006fc:	f9400bf3 	ldr	x19, [sp, #16]
  400700:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400704:	d65f03c0 	ret

0000000000400708 <frame_dummy>:
  400708:	17ffffe6 	b	4006a0 <register_tm_clones>

000000000040070c <creat>:
  40070c:	d10d43ff 	sub	sp, sp, #0x350
  400710:	a9007bfd 	stp	x29, x30, [sp]
  400714:	910003fd 	mov	x29, sp
  400718:	52800020 	mov	w0, #0x1                   	// #1
  40071c:	b9033fa0 	str	w0, [x29, #828]
  400720:	b9033bbf 	str	wzr, [x29, #824]
  400724:	f901a3bf 	str	xzr, [x29, #832]
  400728:	91005fa1 	add	x1, x29, #0x17
  40072c:	90000000 	adrp	x0, 400000 <_init-0x568>
  400730:	913ea000 	add	x0, x0, #0xfa8
  400734:	97ffffab 	bl	4005e0 <__isoc99_scanf@plt>
  400738:	14000044 	b	400848 <creat+0x13c>
  40073c:	f901a7bf 	str	xzr, [x29, #840]
  400740:	39405fa0 	ldrb	w0, [x29, #23]
  400744:	7100b01f 	cmp	w0, #0x2c
  400748:	54000160 	b.eq	400774 <creat+0x68>  // b.none
  40074c:	d2800300 	mov	x0, #0x18                  	// #24
  400750:	97ffff94 	bl	4005a0 <malloc@plt>
  400754:	f901a7a0 	str	x0, [x29, #840]
  400758:	39405fa1 	ldrb	w1, [x29, #23]
  40075c:	f941a7a0 	ldr	x0, [x29, #840]
  400760:	39000001 	strb	w1, [x0]
  400764:	f941a7a0 	ldr	x0, [x29, #840]
  400768:	f900041f 	str	xzr, [x0, #8]
  40076c:	f941a7a0 	ldr	x0, [x29, #840]
  400770:	f900081f 	str	xzr, [x0, #16]
  400774:	b9433ba0 	ldr	w0, [x29, #824]
  400778:	11000400 	add	w0, w0, #0x1
  40077c:	b9033ba0 	str	w0, [x29, #824]
  400780:	b9833ba0 	ldrsw	x0, [x29, #824]
  400784:	d37df000 	lsl	x0, x0, #3
  400788:	910063a1 	add	x1, x29, #0x18
  40078c:	f941a7a2 	ldr	x2, [x29, #840]
  400790:	f8206822 	str	x2, [x1, x0]
  400794:	b9433ba0 	ldr	w0, [x29, #824]
  400798:	7100041f 	cmp	w0, #0x1
  40079c:	54000081 	b.ne	4007ac <creat+0xa0>  // b.any
  4007a0:	f941a7a0 	ldr	x0, [x29, #840]
  4007a4:	f901a3a0 	str	x0, [x29, #832]
  4007a8:	14000024 	b	400838 <creat+0x12c>
  4007ac:	f941a7a0 	ldr	x0, [x29, #840]
  4007b0:	f100001f 	cmp	x0, #0x0
  4007b4:	54000300 	b.eq	400814 <creat+0x108>  // b.none
  4007b8:	b9833fa0 	ldrsw	x0, [x29, #828]
  4007bc:	d37df000 	lsl	x0, x0, #3
  4007c0:	910063a1 	add	x1, x29, #0x18
  4007c4:	f8606820 	ldr	x0, [x1, x0]
  4007c8:	f100001f 	cmp	x0, #0x0
  4007cc:	54000240 	b.eq	400814 <creat+0x108>  // b.none
  4007d0:	b9433ba0 	ldr	w0, [x29, #824]
  4007d4:	12000000 	and	w0, w0, #0x1
  4007d8:	7100001f 	cmp	w0, #0x0
  4007dc:	54000101 	b.ne	4007fc <creat+0xf0>  // b.any
  4007e0:	b9833fa0 	ldrsw	x0, [x29, #828]
  4007e4:	d37df000 	lsl	x0, x0, #3
  4007e8:	910063a1 	add	x1, x29, #0x18
  4007ec:	f8606820 	ldr	x0, [x1, x0]
  4007f0:	f941a7a1 	ldr	x1, [x29, #840]
  4007f4:	f9000401 	str	x1, [x0, #8]
  4007f8:	14000007 	b	400814 <creat+0x108>
  4007fc:	b9833fa0 	ldrsw	x0, [x29, #828]
  400800:	d37df000 	lsl	x0, x0, #3
  400804:	910063a1 	add	x1, x29, #0x18
  400808:	f8606820 	ldr	x0, [x1, x0]
  40080c:	f941a7a1 	ldr	x1, [x29, #840]
  400810:	f9000801 	str	x1, [x0, #16]
  400814:	b9433ba0 	ldr	w0, [x29, #824]
  400818:	7100001f 	cmp	w0, #0x0
  40081c:	12000000 	and	w0, w0, #0x1
  400820:	5a80a400 	cneg	w0, w0, lt  // lt = tstop
  400824:	7100041f 	cmp	w0, #0x1
  400828:	54000081 	b.ne	400838 <creat+0x12c>  // b.any
  40082c:	b9433fa0 	ldr	w0, [x29, #828]
  400830:	11000400 	add	w0, w0, #0x1
  400834:	b9033fa0 	str	w0, [x29, #828]
  400838:	91005fa1 	add	x1, x29, #0x17
  40083c:	90000000 	adrp	x0, 400000 <_init-0x568>
  400840:	913ea000 	add	x0, x0, #0xfa8
  400844:	97ffff67 	bl	4005e0 <__isoc99_scanf@plt>
  400848:	39405fa0 	ldrb	w0, [x29, #23]
  40084c:	71008c1f 	cmp	w0, #0x23
  400850:	54fff761 	b.ne	40073c <creat+0x30>  // b.any
  400854:	f941a3a0 	ldr	x0, [x29, #832]
  400858:	a9407bfd 	ldp	x29, x30, [sp]
  40085c:	910d43ff 	add	sp, sp, #0x350
  400860:	d65f03c0 	ret

0000000000400864 <preorder_r>:
  400864:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400868:	910003fd 	mov	x29, sp
  40086c:	f9000fa0 	str	x0, [x29, #24]
  400870:	f9400fa0 	ldr	x0, [x29, #24]
  400874:	f90017a0 	str	x0, [x29, #40]
  400878:	f94017a0 	ldr	x0, [x29, #40]
  40087c:	f100001f 	cmp	x0, #0x0
  400880:	540001a0 	b.eq	4008b4 <preorder_r+0x50>  // b.none
  400884:	f94017a0 	ldr	x0, [x29, #40]
  400888:	39400000 	ldrb	w0, [x0]
  40088c:	2a0003e1 	mov	w1, w0
  400890:	90000000 	adrp	x0, 400000 <_init-0x568>
  400894:	913ec000 	add	x0, x0, #0xfb0
  400898:	97ffff56 	bl	4005f0 <printf@plt>
  40089c:	f94017a0 	ldr	x0, [x29, #40]
  4008a0:	f9400400 	ldr	x0, [x0, #8]
  4008a4:	97fffff0 	bl	400864 <preorder_r>
  4008a8:	f94017a0 	ldr	x0, [x29, #40]
  4008ac:	f9400800 	ldr	x0, [x0, #16]
  4008b0:	97ffffed 	bl	400864 <preorder_r>
  4008b4:	d503201f 	nop
  4008b8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008bc:	d65f03c0 	ret

00000000004008c0 <preorder>:
  4008c0:	d10d43ff 	sub	sp, sp, #0x350
  4008c4:	a9007bfd 	stp	x29, x30, [sp]
  4008c8:	910003fd 	mov	x29, sp
  4008cc:	f9000fa0 	str	x0, [x29, #24]
  4008d0:	b90347bf 	str	wzr, [x29, #836]
  4008d4:	f9400fa0 	ldr	x0, [x29, #24]
  4008d8:	f901a7a0 	str	x0, [x29, #840]
  4008dc:	14000020 	b	40095c <preorder+0x9c>
  4008e0:	f941a7a0 	ldr	x0, [x29, #840]
  4008e4:	39400000 	ldrb	w0, [x0]
  4008e8:	2a0003e1 	mov	w1, w0
  4008ec:	90000000 	adrp	x0, 400000 <_init-0x568>
  4008f0:	913ec000 	add	x0, x0, #0xfb0
  4008f4:	97ffff3f 	bl	4005f0 <printf@plt>
  4008f8:	b94347a0 	ldr	w0, [x29, #836]
  4008fc:	11000400 	add	w0, w0, #0x1
  400900:	b90347a0 	str	w0, [x29, #836]
  400904:	b98347a0 	ldrsw	x0, [x29, #836]
  400908:	d37df000 	lsl	x0, x0, #3
  40090c:	910083a1 	add	x1, x29, #0x20
  400910:	f941a7a2 	ldr	x2, [x29, #840]
  400914:	f8206822 	str	x2, [x1, x0]
  400918:	f941a7a0 	ldr	x0, [x29, #840]
  40091c:	f9400400 	ldr	x0, [x0, #8]
  400920:	f901a7a0 	str	x0, [x29, #840]
  400924:	f941a7a0 	ldr	x0, [x29, #840]
  400928:	f100001f 	cmp	x0, #0x0
  40092c:	54fffda1 	b.ne	4008e0 <preorder+0x20>  // b.any
  400930:	b94347a0 	ldr	w0, [x29, #836]
  400934:	51000401 	sub	w1, w0, #0x1
  400938:	b90347a1 	str	w1, [x29, #836]
  40093c:	93407c00 	sxtw	x0, w0
  400940:	d37df000 	lsl	x0, x0, #3
  400944:	910083a1 	add	x1, x29, #0x20
  400948:	f8606820 	ldr	x0, [x1, x0]
  40094c:	f901a7a0 	str	x0, [x29, #840]
  400950:	f941a7a0 	ldr	x0, [x29, #840]
  400954:	f9400800 	ldr	x0, [x0, #16]
  400958:	f901a7a0 	str	x0, [x29, #840]
  40095c:	f941a7a0 	ldr	x0, [x29, #840]
  400960:	f100001f 	cmp	x0, #0x0
  400964:	54fffe01 	b.ne	400924 <preorder+0x64>  // b.any
  400968:	b94347a0 	ldr	w0, [x29, #836]
  40096c:	7100001f 	cmp	w0, #0x0
  400970:	54fffdac 	b.gt	400924 <preorder+0x64>
  400974:	d503201f 	nop
  400978:	a9407bfd 	ldp	x29, x30, [sp]
  40097c:	910d43ff 	add	sp, sp, #0x350
  400980:	d65f03c0 	ret

0000000000400984 <inorder_r>:
  400984:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400988:	910003fd 	mov	x29, sp
  40098c:	f9000fa0 	str	x0, [x29, #24]
  400990:	f9400fa0 	ldr	x0, [x29, #24]
  400994:	f90017a0 	str	x0, [x29, #40]
  400998:	f94017a0 	ldr	x0, [x29, #40]
  40099c:	f100001f 	cmp	x0, #0x0
  4009a0:	540001a0 	b.eq	4009d4 <inorder_r+0x50>  // b.none
  4009a4:	f94017a0 	ldr	x0, [x29, #40]
  4009a8:	f9400400 	ldr	x0, [x0, #8]
  4009ac:	97fffff6 	bl	400984 <inorder_r>
  4009b0:	f94017a0 	ldr	x0, [x29, #40]
  4009b4:	39400000 	ldrb	w0, [x0]
  4009b8:	2a0003e1 	mov	w1, w0
  4009bc:	90000000 	adrp	x0, 400000 <_init-0x568>
  4009c0:	913ec000 	add	x0, x0, #0xfb0
  4009c4:	97ffff0b 	bl	4005f0 <printf@plt>
  4009c8:	f94017a0 	ldr	x0, [x29, #40]
  4009cc:	f9400800 	ldr	x0, [x0, #16]
  4009d0:	97ffffed 	bl	400984 <inorder_r>
  4009d4:	d503201f 	nop
  4009d8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4009dc:	d65f03c0 	ret

00000000004009e0 <inorder>:
  4009e0:	d10d43ff 	sub	sp, sp, #0x350
  4009e4:	a9007bfd 	stp	x29, x30, [sp]
  4009e8:	910003fd 	mov	x29, sp
  4009ec:	f9000fa0 	str	x0, [x29, #24]
  4009f0:	b90347bf 	str	wzr, [x29, #836]
  4009f4:	f9400fa0 	ldr	x0, [x29, #24]
  4009f8:	f901a7a0 	str	x0, [x29, #840]
  4009fc:	14000020 	b	400a7c <inorder+0x9c>
  400a00:	b94347a0 	ldr	w0, [x29, #836]
  400a04:	11000400 	add	w0, w0, #0x1
  400a08:	b90347a0 	str	w0, [x29, #836]
  400a0c:	b98347a0 	ldrsw	x0, [x29, #836]
  400a10:	d37df000 	lsl	x0, x0, #3
  400a14:	910083a1 	add	x1, x29, #0x20
  400a18:	f941a7a2 	ldr	x2, [x29, #840]
  400a1c:	f8206822 	str	x2, [x1, x0]
  400a20:	f941a7a0 	ldr	x0, [x29, #840]
  400a24:	f9400400 	ldr	x0, [x0, #8]
  400a28:	f901a7a0 	str	x0, [x29, #840]
  400a2c:	f941a7a0 	ldr	x0, [x29, #840]
  400a30:	f100001f 	cmp	x0, #0x0
  400a34:	54fffe61 	b.ne	400a00 <inorder+0x20>  // b.any
  400a38:	b94347a0 	ldr	w0, [x29, #836]
  400a3c:	51000401 	sub	w1, w0, #0x1
  400a40:	b90347a1 	str	w1, [x29, #836]
  400a44:	93407c00 	sxtw	x0, w0
  400a48:	d37df000 	lsl	x0, x0, #3
  400a4c:	910083a1 	add	x1, x29, #0x20
  400a50:	f8606820 	ldr	x0, [x1, x0]
  400a54:	f901a7a0 	str	x0, [x29, #840]
  400a58:	f941a7a0 	ldr	x0, [x29, #840]
  400a5c:	39400000 	ldrb	w0, [x0]
  400a60:	2a0003e1 	mov	w1, w0
  400a64:	90000000 	adrp	x0, 400000 <_init-0x568>
  400a68:	913ec000 	add	x0, x0, #0xfb0
  400a6c:	97fffee1 	bl	4005f0 <printf@plt>
  400a70:	f941a7a0 	ldr	x0, [x29, #840]
  400a74:	f9400800 	ldr	x0, [x0, #16]
  400a78:	f901a7a0 	str	x0, [x29, #840]
  400a7c:	f941a7a0 	ldr	x0, [x29, #840]
  400a80:	f100001f 	cmp	x0, #0x0
  400a84:	54fffd41 	b.ne	400a2c <inorder+0x4c>  // b.any
  400a88:	b94347a0 	ldr	w0, [x29, #836]
  400a8c:	7100001f 	cmp	w0, #0x0
  400a90:	54fffcec 	b.gt	400a2c <inorder+0x4c>
  400a94:	d503201f 	nop
  400a98:	a9407bfd 	ldp	x29, x30, [sp]
  400a9c:	910d43ff 	add	sp, sp, #0x350
  400aa0:	d65f03c0 	ret

0000000000400aa4 <postorder_r>:
  400aa4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400aa8:	910003fd 	mov	x29, sp
  400aac:	f9000fa0 	str	x0, [x29, #24]
  400ab0:	f9400fa0 	ldr	x0, [x29, #24]
  400ab4:	f90017a0 	str	x0, [x29, #40]
  400ab8:	f94017a0 	ldr	x0, [x29, #40]
  400abc:	f100001f 	cmp	x0, #0x0
  400ac0:	540001a0 	b.eq	400af4 <postorder_r+0x50>  // b.none
  400ac4:	f94017a0 	ldr	x0, [x29, #40]
  400ac8:	f9400400 	ldr	x0, [x0, #8]
  400acc:	97fffff6 	bl	400aa4 <postorder_r>
  400ad0:	f94017a0 	ldr	x0, [x29, #40]
  400ad4:	f9400800 	ldr	x0, [x0, #16]
  400ad8:	97fffff3 	bl	400aa4 <postorder_r>
  400adc:	f94017a0 	ldr	x0, [x29, #40]
  400ae0:	39400000 	ldrb	w0, [x0]
  400ae4:	2a0003e1 	mov	w1, w0
  400ae8:	90000000 	adrp	x0, 400000 <_init-0x568>
  400aec:	913ec000 	add	x0, x0, #0xfb0
  400af0:	97fffec0 	bl	4005f0 <printf@plt>
  400af4:	d503201f 	nop
  400af8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400afc:	d65f03c0 	ret

0000000000400b00 <postorder>:
  400b00:	d11383ff 	sub	sp, sp, #0x4e0
  400b04:	a9007bfd 	stp	x29, x30, [sp]
  400b08:	910003fd 	mov	x29, sp
  400b0c:	f9000fa0 	str	x0, [x29, #24]
  400b10:	b904d7bf 	str	wzr, [x29, #1236]
  400b14:	f9400fa0 	ldr	x0, [x29, #24]
  400b18:	f9026fa0 	str	x0, [x29, #1240]
  400b1c:	14000010 	b	400b5c <postorder+0x5c>
  400b20:	b984d7a0 	ldrsw	x0, [x29, #1236]
  400b24:	d37df000 	lsl	x0, x0, #3
  400b28:	9106c3a1 	add	x1, x29, #0x1b0
  400b2c:	f9426fa2 	ldr	x2, [x29, #1240]
  400b30:	f8206822 	str	x2, [x1, x0]
  400b34:	b944d7a0 	ldr	w0, [x29, #1236]
  400b38:	11000401 	add	w1, w0, #0x1
  400b3c:	b904d7a1 	str	w1, [x29, #1236]
  400b40:	93407c00 	sxtw	x0, w0
  400b44:	d37ef400 	lsl	x0, x0, #2
  400b48:	910083a1 	add	x1, x29, #0x20
  400b4c:	b820683f 	str	wzr, [x1, x0]
  400b50:	f9426fa0 	ldr	x0, [x29, #1240]
  400b54:	f9400400 	ldr	x0, [x0, #8]
  400b58:	f9026fa0 	str	x0, [x29, #1240]
  400b5c:	f9426fa0 	ldr	x0, [x29, #1240]
  400b60:	f100001f 	cmp	x0, #0x0
  400b64:	54fffde1 	b.ne	400b20 <postorder+0x20>  // b.any
  400b68:	b944d7a0 	ldr	w0, [x29, #1236]
  400b6c:	7100001f 	cmp	w0, #0x0
  400b70:	5400052d 	b.le	400c14 <postorder+0x114>
  400b74:	b944d7a0 	ldr	w0, [x29, #1236]
  400b78:	51000400 	sub	w0, w0, #0x1
  400b7c:	b904d7a0 	str	w0, [x29, #1236]
  400b80:	b984d7a0 	ldrsw	x0, [x29, #1236]
  400b84:	d37ef400 	lsl	x0, x0, #2
  400b88:	910083a1 	add	x1, x29, #0x20
  400b8c:	b8606820 	ldr	w0, [x1, x0]
  400b90:	b904d3a0 	str	w0, [x29, #1232]
  400b94:	b984d7a0 	ldrsw	x0, [x29, #1236]
  400b98:	d37df000 	lsl	x0, x0, #3
  400b9c:	9106c3a1 	add	x1, x29, #0x1b0
  400ba0:	f8606820 	ldr	x0, [x1, x0]
  400ba4:	f9026fa0 	str	x0, [x29, #1240]
  400ba8:	b944d3a0 	ldr	w0, [x29, #1232]
  400bac:	7100001f 	cmp	w0, #0x0
  400bb0:	54000241 	b.ne	400bf8 <postorder+0xf8>  // b.any
  400bb4:	b984d7a0 	ldrsw	x0, [x29, #1236]
  400bb8:	d37df000 	lsl	x0, x0, #3
  400bbc:	9106c3a1 	add	x1, x29, #0x1b0
  400bc0:	f9426fa2 	ldr	x2, [x29, #1240]
  400bc4:	f8206822 	str	x2, [x1, x0]
  400bc8:	b944d7a0 	ldr	w0, [x29, #1236]
  400bcc:	11000401 	add	w1, w0, #0x1
  400bd0:	b904d7a1 	str	w1, [x29, #1236]
  400bd4:	93407c00 	sxtw	x0, w0
  400bd8:	d37ef400 	lsl	x0, x0, #2
  400bdc:	910083a1 	add	x1, x29, #0x20
  400be0:	52800022 	mov	w2, #0x1                   	// #1
  400be4:	b8206822 	str	w2, [x1, x0]
  400be8:	f9426fa0 	ldr	x0, [x29, #1240]
  400bec:	f9400800 	ldr	x0, [x0, #16]
  400bf0:	f9026fa0 	str	x0, [x29, #1240]
  400bf4:	14000008 	b	400c14 <postorder+0x114>
  400bf8:	f9426fa0 	ldr	x0, [x29, #1240]
  400bfc:	39400000 	ldrb	w0, [x0]
  400c00:	2a0003e1 	mov	w1, w0
  400c04:	90000000 	adrp	x0, 400000 <_init-0x568>
  400c08:	913ec000 	add	x0, x0, #0xfb0
  400c0c:	97fffe79 	bl	4005f0 <printf@plt>
  400c10:	f9026fbf 	str	xzr, [x29, #1240]
  400c14:	b944d7a0 	ldr	w0, [x29, #1236]
  400c18:	7100001f 	cmp	w0, #0x0
  400c1c:	54fffa0c 	b.gt	400b5c <postorder+0x5c>
  400c20:	d503201f 	nop
  400c24:	a9407bfd 	ldp	x29, x30, [sp]
  400c28:	911383ff 	add	sp, sp, #0x4e0
  400c2c:	d65f03c0 	ret

0000000000400c30 <treehigh>:
  400c30:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400c34:	910003fd 	mov	x29, sp
  400c38:	f9000fa0 	str	x0, [x29, #24]
  400c3c:	f9400fa0 	ldr	x0, [x29, #24]
  400c40:	f100001f 	cmp	x0, #0x0
  400c44:	54000061 	b.ne	400c50 <treehigh+0x20>  // b.any
  400c48:	b9002fbf 	str	wzr, [x29, #44]
  400c4c:	14000014 	b	400c9c <treehigh+0x6c>
  400c50:	f9400fa0 	ldr	x0, [x29, #24]
  400c54:	f9400400 	ldr	x0, [x0, #8]
  400c58:	97fffff6 	bl	400c30 <treehigh>
  400c5c:	b9002ba0 	str	w0, [x29, #40]
  400c60:	f9400fa0 	ldr	x0, [x29, #24]
  400c64:	f9400800 	ldr	x0, [x0, #16]
  400c68:	97fffff2 	bl	400c30 <treehigh>
  400c6c:	b90027a0 	str	w0, [x29, #36]
  400c70:	b9402ba1 	ldr	w1, [x29, #40]
  400c74:	b94027a0 	ldr	w0, [x29, #36]
  400c78:	6b00003f 	cmp	w1, w0
  400c7c:	540000ab 	b.lt	400c90 <treehigh+0x60>  // b.tstop
  400c80:	b9402ba0 	ldr	w0, [x29, #40]
  400c84:	11000400 	add	w0, w0, #0x1
  400c88:	b9002fa0 	str	w0, [x29, #44]
  400c8c:	14000004 	b	400c9c <treehigh+0x6c>
  400c90:	b94027a0 	ldr	w0, [x29, #36]
  400c94:	11000400 	add	w0, w0, #0x1
  400c98:	b9002fa0 	str	w0, [x29, #44]
  400c9c:	b9402fa0 	ldr	w0, [x29, #44]
  400ca0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ca4:	d65f03c0 	ret

0000000000400ca8 <traverse>:
  400ca8:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400cac:	910003fd 	mov	x29, sp
  400cb0:	f9000fa0 	str	x0, [x29, #24]
  400cb4:	39005fa1 	strb	w1, [x29, #23]
  400cb8:	f90017bf 	str	xzr, [x29, #40]
  400cbc:	f9400fa0 	ldr	x0, [x29, #24]
  400cc0:	f100001f 	cmp	x0, #0x0
  400cc4:	54000240 	b.eq	400d0c <traverse+0x64>  // b.none
  400cc8:	f9400fa0 	ldr	x0, [x29, #24]
  400ccc:	39400000 	ldrb	w0, [x0]
  400cd0:	39405fa1 	ldrb	w1, [x29, #23]
  400cd4:	6b00003f 	cmp	w1, w0
  400cd8:	540000a1 	b.ne	400cec <traverse+0x44>  // b.any
  400cdc:	f9400fa0 	ldr	x0, [x29, #24]
  400ce0:	f90017a0 	str	x0, [x29, #40]
  400ce4:	f94017a0 	ldr	x0, [x29, #40]
  400ce8:	14000009 	b	400d0c <traverse+0x64>
  400cec:	f9400fa0 	ldr	x0, [x29, #24]
  400cf0:	f9400400 	ldr	x0, [x0, #8]
  400cf4:	39405fa1 	ldrb	w1, [x29, #23]
  400cf8:	97ffffec 	bl	400ca8 <traverse>
  400cfc:	f9400fa0 	ldr	x0, [x29, #24]
  400d00:	f9400800 	ldr	x0, [x0, #16]
  400d04:	39405fa1 	ldrb	w1, [x29, #23]
  400d08:	97ffffe8 	bl	400ca8 <traverse>
  400d0c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400d10:	d65f03c0 	ret

0000000000400d14 <find>:
  400d14:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400d18:	910003fd 	mov	x29, sp
  400d1c:	f9000fa0 	str	x0, [x29, #24]
  400d20:	39005fa1 	strb	w1, [x29, #23]
  400d24:	39405fa1 	ldrb	w1, [x29, #23]
  400d28:	f9400fa0 	ldr	x0, [x29, #24]
  400d2c:	97ffffdf 	bl	400ca8 <traverse>
  400d30:	f90017a0 	str	x0, [x29, #40]
  400d34:	f94017a0 	ldr	x0, [x29, #40]
  400d38:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400d3c:	d65f03c0 	ret

0000000000400d40 <leaf>:
  400d40:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400d44:	910003fd 	mov	x29, sp
  400d48:	f9000fa0 	str	x0, [x29, #24]
  400d4c:	b90017a1 	str	w1, [x29, #20]
  400d50:	f9400fa0 	ldr	x0, [x29, #24]
  400d54:	f100001f 	cmp	x0, #0x0
  400d58:	540002c0 	b.eq	400db0 <leaf+0x70>  // b.none
  400d5c:	f9400fa0 	ldr	x0, [x29, #24]
  400d60:	f9400400 	ldr	x0, [x0, #8]
  400d64:	f100001f 	cmp	x0, #0x0
  400d68:	54000101 	b.ne	400d88 <leaf+0x48>  // b.any
  400d6c:	f9400fa0 	ldr	x0, [x29, #24]
  400d70:	f9400800 	ldr	x0, [x0, #16]
  400d74:	f100001f 	cmp	x0, #0x0
  400d78:	54000081 	b.ne	400d88 <leaf+0x48>  // b.any
  400d7c:	b94017a0 	ldr	w0, [x29, #20]
  400d80:	11000400 	add	w0, w0, #0x1
  400d84:	b90017a0 	str	w0, [x29, #20]
  400d88:	f9400fa0 	ldr	x0, [x29, #24]
  400d8c:	f9400400 	ldr	x0, [x0, #8]
  400d90:	b94017a1 	ldr	w1, [x29, #20]
  400d94:	97ffffeb 	bl	400d40 <leaf>
  400d98:	b90017a0 	str	w0, [x29, #20]
  400d9c:	f9400fa0 	ldr	x0, [x29, #24]
  400da0:	f9400800 	ldr	x0, [x0, #16]
  400da4:	b94017a1 	ldr	w1, [x29, #20]
  400da8:	97ffffe6 	bl	400d40 <leaf>
  400dac:	b90017a0 	str	w0, [x29, #20]
  400db0:	d503201f 	nop
  400db4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400db8:	d65f03c0 	ret

0000000000400dbc <lorder>:
  400dbc:	d10d43ff 	sub	sp, sp, #0x350
  400dc0:	a9007bfd 	stp	x29, x30, [sp]
  400dc4:	910003fd 	mov	x29, sp
  400dc8:	f9000fa0 	str	x0, [x29, #24]
  400dcc:	f9400fa0 	ldr	x0, [x29, #24]
  400dd0:	f90017a0 	str	x0, [x29, #40]
  400dd4:	52800020 	mov	w0, #0x1                   	// #1
  400dd8:	b9034fa0 	str	w0, [x29, #844]
  400ddc:	52800020 	mov	w0, #0x1                   	// #1
  400de0:	b9034ba0 	str	w0, [x29, #840]
  400de4:	14000029 	b	400e88 <lorder+0xcc>
  400de8:	b9834fa0 	ldrsw	x0, [x29, #844]
  400dec:	d37df000 	lsl	x0, x0, #3
  400df0:	910083a1 	add	x1, x29, #0x20
  400df4:	f8606820 	ldr	x0, [x1, x0]
  400df8:	f901a3a0 	str	x0, [x29, #832]
  400dfc:	b9434fa0 	ldr	w0, [x29, #844]
  400e00:	11000400 	add	w0, w0, #0x1
  400e04:	b9034fa0 	str	w0, [x29, #844]
  400e08:	f941a3a0 	ldr	x0, [x29, #832]
  400e0c:	39400000 	ldrb	w0, [x0]
  400e10:	2a0003e1 	mov	w1, w0
  400e14:	90000000 	adrp	x0, 400000 <_init-0x568>
  400e18:	913ee000 	add	x0, x0, #0xfb8
  400e1c:	97fffdf5 	bl	4005f0 <printf@plt>
  400e20:	f941a3a0 	ldr	x0, [x29, #832]
  400e24:	f9400400 	ldr	x0, [x0, #8]
  400e28:	f100001f 	cmp	x0, #0x0
  400e2c:	54000140 	b.eq	400e54 <lorder+0x98>  // b.none
  400e30:	b9434ba0 	ldr	w0, [x29, #840]
  400e34:	11000400 	add	w0, w0, #0x1
  400e38:	b9034ba0 	str	w0, [x29, #840]
  400e3c:	f941a3a0 	ldr	x0, [x29, #832]
  400e40:	f9400402 	ldr	x2, [x0, #8]
  400e44:	b9834ba0 	ldrsw	x0, [x29, #840]
  400e48:	d37df000 	lsl	x0, x0, #3
  400e4c:	910083a1 	add	x1, x29, #0x20
  400e50:	f8206822 	str	x2, [x1, x0]
  400e54:	f941a3a0 	ldr	x0, [x29, #832]
  400e58:	f9400800 	ldr	x0, [x0, #16]
  400e5c:	f100001f 	cmp	x0, #0x0
  400e60:	54000140 	b.eq	400e88 <lorder+0xcc>  // b.none
  400e64:	b9434ba0 	ldr	w0, [x29, #840]
  400e68:	11000400 	add	w0, w0, #0x1
  400e6c:	b9034ba0 	str	w0, [x29, #840]
  400e70:	f941a3a0 	ldr	x0, [x29, #832]
  400e74:	f9400802 	ldr	x2, [x0, #16]
  400e78:	b9834ba0 	ldrsw	x0, [x29, #840]
  400e7c:	d37df000 	lsl	x0, x0, #3
  400e80:	910083a1 	add	x1, x29, #0x20
  400e84:	f8206822 	str	x2, [x1, x0]
  400e88:	b9434fa1 	ldr	w1, [x29, #844]
  400e8c:	b9434ba0 	ldr	w0, [x29, #840]
  400e90:	6b00003f 	cmp	w1, w0
  400e94:	54fffaad 	b.le	400de8 <lorder+0x2c>
  400e98:	d503201f 	nop
  400e9c:	a9407bfd 	ldp	x29, x30, [sp]
  400ea0:	910d43ff 	add	sp, sp, #0x350
  400ea4:	d65f03c0 	ret

0000000000400ea8 <main>:
  400ea8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400eac:	910003fd 	mov	x29, sp
  400eb0:	97fffe17 	bl	40070c <creat>
  400eb4:	f9000fa0 	str	x0, [x29, #24]
  400eb8:	f9400fa0 	ldr	x0, [x29, #24]
  400ebc:	97fffe81 	bl	4008c0 <preorder>
  400ec0:	52800140 	mov	w0, #0xa                   	// #10
  400ec4:	97fffdcf 	bl	400600 <putchar@plt>
  400ec8:	f9400fa0 	ldr	x0, [x29, #24]
  400ecc:	97fffeae 	bl	400984 <inorder_r>
  400ed0:	52800140 	mov	w0, #0xa                   	// #10
  400ed4:	97fffdcb 	bl	400600 <putchar@plt>
  400ed8:	f9400fa0 	ldr	x0, [x29, #24]
  400edc:	97fffef2 	bl	400aa4 <postorder_r>
  400ee0:	52800140 	mov	w0, #0xa                   	// #10
  400ee4:	97fffdc7 	bl	400600 <putchar@plt>
  400ee8:	52800000 	mov	w0, #0x0                   	// #0
  400eec:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400ef0:	d65f03c0 	ret
  400ef4:	00000000 	.inst	0x00000000 ; undefined

0000000000400ef8 <__libc_csu_init>:
  400ef8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400efc:	910003fd 	mov	x29, sp
  400f00:	a901d7f4 	stp	x20, x21, [sp, #24]
  400f04:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10040>
  400f08:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10040>
  400f0c:	91374294 	add	x20, x20, #0xdd0
  400f10:	913722b5 	add	x21, x21, #0xdc8
  400f14:	a902dff6 	stp	x22, x23, [sp, #40]
  400f18:	cb150294 	sub	x20, x20, x21
  400f1c:	f9001ff8 	str	x24, [sp, #56]
  400f20:	2a0003f6 	mov	w22, w0
  400f24:	aa0103f7 	mov	x23, x1
  400f28:	9343fe94 	asr	x20, x20, #3
  400f2c:	aa0203f8 	mov	x24, x2
  400f30:	97fffd8e 	bl	400568 <_init>
  400f34:	b4000194 	cbz	x20, 400f64 <__libc_csu_init+0x6c>
  400f38:	f9000bb3 	str	x19, [x29, #16]
  400f3c:	d2800013 	mov	x19, #0x0                   	// #0
  400f40:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400f44:	aa1803e2 	mov	x2, x24
  400f48:	aa1703e1 	mov	x1, x23
  400f4c:	2a1603e0 	mov	w0, w22
  400f50:	91000673 	add	x19, x19, #0x1
  400f54:	d63f0060 	blr	x3
  400f58:	eb13029f 	cmp	x20, x19
  400f5c:	54ffff21 	b.ne	400f40 <__libc_csu_init+0x48>  // b.any
  400f60:	f9400bb3 	ldr	x19, [x29, #16]
  400f64:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400f68:	a942dff6 	ldp	x22, x23, [sp, #40]
  400f6c:	f9401ff8 	ldr	x24, [sp, #56]
  400f70:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400f74:	d65f03c0 	ret

0000000000400f78 <__libc_csu_fini>:
  400f78:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400f7c <_fini>:
  400f7c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400f80:	910003fd 	mov	x29, sp
  400f84:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400f88:	d65f03c0 	ret
